1. Field of the Invention
The present invention relates to a liquid crystal display controller, and more particularly to processing during the occurrence of abnormal conditions in a synchronizing signal.
2. Description of the Related Art
A liquid crystal display panel (LCD panel) which has conventionally been used as a monitor for a personal computer (PC) is now, in a growing number of cases, used for a liquid crystal television capitalizing on its thin and lightweight features. As long as a LCD panel is used as a PC monitor, a relatively stable signal is input to the LCD panel. On the other hand, when the LCD panel is used as a liquid crystal television, an input signal becomes unstable during channel tuning, and reproduction, fast-forwarding, and rewinding of VTR.
FIG. 8 shows a structure of a typical liquid crystal television. The liquid crystal television comprises a TV tuner 10 for receiving a TV image signal, an RGB decoder 12 for extracting an R signal, a G signal, and a B signal from the TV image signal received, a scaler 14 for converting the number of horizontal pixels or the number of scanning lines in the TV image signal, and a panel module 16. The panel module 16 includes a LCD panel and a LCD controller for driving the LCD panel. The LCD controller includes a timing controller for controlling timing and a driver IC, and scans the LCD panel in synchronism with horizontal and vertical synchronization signals. The driver IC latches a digital image signal in one horizontal period into a latch circuit based on a latch signal STB from the timing controller, and after converting the digital image signal into an analog signal in a D/A converter, outputs the analog signal to a driver element for driving each pixel of the LCD panel. For example, digital image signal data of R, G, and B stored in a data register is transferred to and latched into the latch circuit at the rising edge of the latch signal STB, and then analog output is sent to and displayed on the LCD panel at the falling edge of STB.
The timing controller and the driver IC properly operate whenever a stable signal is supplied from the PC or the like, whereas the timing controller cannot properly operate to drive the LCD panel when an unstable signal is supplied, as is often the case in channel tuning, VTR reproduction, etc. Such improper driving of the LCD panel results in that the screen becomes full white (in the case of a normally-white screen) or full black (in the case of a normally-black screen). The state where an unstable signal, in particular, a signal in which periods of horizontal and vertical synchronization signals are abnormal, is supplied, thereby causing a LCD panel to become full white or full black is specifically referred to as “burning” in the specification of this application.
Such “burning” can be prevented by adding a circuit in which the periods of the horizontal and vertical synchronization signals to be supplied to the LCD controller are detected to correct a period which is found to be different from a normal period.
Japanese Patent Laid-Open Publication No. Hei 10-49057 describes technology of masking new input of a vertical synchronization signal when a period of the vertical synchronization signal is shorter than a predetermined period, and further describes the following technique. If new input of the vertical synchronization signal is not supplied over a predetermined length of time after the last input of the vertical synchronization signal, a preliminary pulse is generated with the period equal to that of the vertical synchronization signal in the immediately preceding frame, and if the period between the preliminary pulse and new input of the vertical synchronization signal immediately subsequent to the preliminary pulse is shorter than a predetermined period, the new input of the vertical synchronization signal is masked.
FIG. 9 shows a configuration of a vertical count-down circuit employing the above-described technology and FIG. 10 shows a timing chart for the circuit. Suppose that a signal including a period shorter than the normal period is input to an AND circuit 70 as a vertical synchronization signal. Further, assuming output of an OR circuit 73 to be shifted to an “L” state by the first pulse of the vertical synchronization signal shown in FIG. 10, a counter 74 outputs a count value read at that time to a delay inverter 77, and resets the count value to “0” to initiate count up operation. The delay inverter 77 changes the sign of the count value output from the counter 74 as well as delaying the count value by one frame, and then outputs resulting data to a counter 75. The counter 75 initiates its count up operation taking the data output from the delay inverter 77 as an initial value. When the count value of the counter 74 reaches or exceeds “480”, a window signal for noise removal to be output from the counter 74 to the AND circuit 70 is set to an “H” state. Then, when the second pulse of the vertical synchronization signal is input, the counters 74 and 75 are reset in synchronism with falling of the pulse. If the period of the vertical synchronization signal is normal, the count value of the counter 74 reads “525” immediately before resetting. This value is output to the delay inverter 77 in which after delaying the count value by one frame, the sign of the value is reversed to read “−525”, and then supplied from the delay inverter 77 to the counter 75. The counter 75 initiates its count up operation taking the value supplied from the delay inverter 77 as an initial value, and sets the output signal to be provided to the OR circuit 78 to an “L” state when the count value reaches “−2” or greater (−2, −1). If the count value reaches “−1”, the output signal to be provided to the counter 76 is set to the “L” state and the count up operation is terminated. The counter 76 sets the output signal to the “H” state at the falling edge of the output signal from the counter 75 and initiates its count up operation from the initial value of “0”. When the count value reaches “480”, the counter 76 sets the output signal to “L” and terminates the count up operation. The output signal from the OR circuit 78 is changed to the “L” state when the output from the counter 75 and the output from the counter 76 both become “L” state. Here, suppose that the fourth pulse of the vertical synchronization signal is input. Because an interval between the third pulse and the fourth pulse is shorter than usual intervals, the fourth pulse will be input to the AND circuit 70 before the count value of the counter 74 reaches “480”. In other words, the fourth pulse is input when the output of the counter 74 is in the “L” state, which results in the fourth pulse being masked by the AND circuit 70. Therefore, a signal corresponding to the fourth pulse would not be output from the OR circuit 78. The counter 76 executes its count up operation after being reset by the third pulse of the vertical synchronization signal, and sets the output signal to the “L” state when the count value reaches “480”. On the other hand, the counter 75 counts up from “−525” which is the count value of the immediately preceding frame and imported into the counter 75 as the initial value, and sets the output to the OR circuit 78 to “L” state at a time of reading a value “−2”. At this time, because the output signal from the counter 76 is already in the “L” state, the output from the OR circuit 78 is set to “L” state (in which the fourth pulse is output). Subsequently the fifth pulse of the vertical synchronization signal is input, which causes the AND circuit 70 to output a pulse because the output from the counter 74 to the AND circuit 70 is in the “H” state when the fifth pulse is input. As a result of output of the pulse, output of a differentiating circuit is set to the “L” state, and as a result the counters 74 and 75 are reset. At the moment of resetting, the output of the counter 75 is in an “L” state, whereas the output of the counter 76 is in an “H” state (because the count value of the counter 76 is smaller than “480”), which brings about no change in the output signal of the OR circuit 78 (the “H” state is maintained). When the sixth pulse of the vertical synchronization signal is subsequently input, the output of the OR circuit 73 is turned to the “L” state because the output of the counter 74 is already in the “H” state. Consequently, the counters 74 and 75 are reset. At the moment of resetting, because the output of the counter 76 has already been set to “L” state, the output of the OR circuit 78 is set to “L” state at the same timing of resetting the counter 75 (i.e. the fifth pulse is output).
In this manner, when the signal including a period which is shorter than the normal period is input, the signal is masked by the counter 74 and the AND circuit 70 to thereby make it possible to avoid feeding of an abnormal synchronization signal.
In the above-described technology, however, masking is executed to prevent an original synchronization signal being output immediately after count down output, while an original synchronization signal input after the expiration of the masking period is taken in and output without change. Therefore, the final period of the vertical synchronization signal will differ from the intrinsic period, which brings about difficulty in driving the LCD panel properly.